Fluent Bit meets RISC-V
Background

Fluent Bit meets RISC-V

Written by Hiroshi Hatake in Fluent Biton January 31, 2023

Fluent Bit meets RISC-V

Recently, the RISC-V (“risk-five”) processor has been receiving a lot of attention from those seeking an alternative to the AArch64 architecture for embedded systems. This is because AArch64 is the 64-bit extension of the ARM architecture family, and while it is efficient and powerful, the architecture is also proprietary.

The RISC-V ecosystem had been supported in LLVM since LLVM 9.0.0. Also, GCC (the GNU Compiler Collections) already supports RISC-V target.

With the growing interest in RISC-V we decided to test Fluent Bit on the architecture. Here’s what we learned.

What is RISC-V?

RISC-V is an open-source Instruction Set Architecture (ISA) created in 2010.

The initial intended usage was for education and research. Today, though, the architecture has become one of the top competitors of ARM. However, unlike ARM, the RISC-V specification is open source.

Users can add additional extensions to the ISA to reduce costs or improve performance. Some extensions are ratified, but users can also add their custom extensions.

Experiment: Running Fluent Bit on RISC-V

The Starfive Tech Vision Five 2 board began shipping with a RISC-V 64-bit processor and PowerVR GPU at the end of last year.

[email protected]:~$ uname -a
Linux starfive 5.15.0-starfive #1 SMP Mon Dec 19 07:56:37 EST 2022 riscv64 GNU/Linux

This board can run Debian 12 “Bookworm” which is currently in testing and is expected to be released later this year.

We tested Fluent Bit with RISC-V on this board with a Debian Bookworm image.

To start this experiment, we had to install the prerequisites to build Fluent Bit with the build from source instructions.

After installing the prerequisites, we proceeded to build Fluent Bit with:

[email protected]:~$ git clone https://github.com/fluent/fluent-bit
[email protected]:~$ cd fluent-bit/build
[email protected]:~$ cmake .. -DFLB_LUAJIT=No
[email protected]:~$ make -j4

Note that we had to specify -DFLB_LUAJIT=No to build Fluent Bit for RISC-V 64bit. The current Fluent Bit bundled version of LuaJIT does not support RISC-V architecture.

After a while, we can build Fluent Bit as a RISC-V application.

[email protected]:~$ file bin/fluent-bit
bin/fluent-bit: ELF 64-bit LSB pie executable, UCB RISC-V, RVC, double-float ABI, version 1 (SYSV), dynamically linked, interpreter /lib/ld-linux-riscv64-lp64d.so.1, BuildID[sha1]=d0a4f8774632374fd8018c29279f4f528dc313b8, for GNU/Linux 4.15.0, with debug_info, not stripped

Support of RISC-V Status

We found that most of the components worked fine, although LuaJIT and Wasm features are restricted on RISC-V.

LuaJIT is not working for now. However, Wasm input and filter can work with AOT (Ahead Of Time) compilation.

Wasm input and filter features should work with AOT objects that are created by:

$ bin/flb-wamrc --target=riscv64 --target-abi=lp64d -o name_of_wasm_prog_riscv64.aot name_of_wasm_prog.wasm

flb-wamrc is an AOT compiler for Wasm. This should be built with -DFLB_WAMRC=On and llvm development packages on ordinary PC boxes.

Conclusion

Supporting RISC-V is an experimental journey for us. As Fluent Bit continues to grow we may need to adopt different platforms from ordinary targets such as x86_64 and AArch64.

Thanks to already matured toolchains for RISC-V, this experiment did not face any huge challenges in getting Fluent Bit executables working on the platform.

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